The present invention relates to semiconductor based memory devices, and in particular to column decoder line routing in semiconductor based memory devices.
Semiconductor memory devices are becoming more and more complex as their size decreases and their storage density increases. To help handle some of the increase in storage density, an architecture comprising multiple subarrays of memory cells on a die for storing values such as bits, has been adopted in dynamic random access memory (DRAM) devices. Each of the subarrays comprises multiple rows of memory cells that are accessed or xe2x80x9cfiredxe2x80x9d by activation of row address signals. Each memory cell in a row in a subarray is coupled via a digit line to its own set of interleaved sense amplifiers which provide the bits to pairs of I/O lines 112, 114, 116 and 118, as shown in prior art FIG. 1. FIG. 1 is an example of a complex twist digit line scheme which helps to reduce coupling terms from each digit line to other digit lines. Each digit line twist occupies valuable silicon area, so efficient twist schemes must be utilized. Column decoder lines 120 and 122 run over a block of memory cells on metal, and connect to I/O switches 124 which enable the sense amplifier to provide a bit or digit sensed and amplified from the digit lines to the I/O lines, Due to layout considerations, a global column decode or coldec line usually allows for two digits in every interleaved sense amplifier block to connect to the I/O lines. Thus, one global column decoder line going high allows four adjacent digits or bits of data to be switched onto four I/O line pairs as seen in prior art FIG. 1.
This type of architecture has been very helpful in obtaining DRAMs beyond the 16 MB generation. However, one global column decoder line going high allows four adjacent digits to be switched onto four I/O line pairs. Note that no other global coldec line can go high along these I/O lines, since this would short together digit pairs through the I/O switches. In this conventional scheme, it is often desired to take these four active bits of data to individual external output pins referred to as DQ pins, allowing each bit to be read or written simultaneously. Because neighboring digits are very capacitively coupled to each other due to their close proximity, writing these four adjacent pairs simultaneously can lead to poor write times. Furthermore, since every combination among the four digits must be tested for proper operation, significant time and complexity is added to testing.
In the past, these problems have often meant that only two of the four I/O lines are simultaneously routed to DQ pins, and these two are further chosen to be two nonadjacent digit lines. Thus, I/O pairs 112 and 116 would be simultaneously active, while I/O pairs 114 and 118 were ignored. The opposite is true when 114 and 118 are active, 112 and 116 are ignored. This solves the write problem, but means that another two bits of data must be taken from another array on the die, which adds to die operating current, size, and complexity, all of which adversely affect cost.
There is a need for increasing the number of simultaneous I/O lines which can be output from a memory array. There is a need for this number to be increased without adding to die operating current, size or complexity. There is a further need to cut down on the time, complexity and expense of testing DRAMs.
Adjacent global column decode lines in a dynamic random access memory (DRAM) array having twisted digit lines are twisted such that one global column decoder line provides access to four non-adjacent digit line pairs. The four non-adjacent digit pairs are routed to external pins, allowing data from each of the pairs to be read or written simultaneously. In one embodiment, selected pairs of digit lines are selectively twisted from inside to outside to ensure that digit lines from different memory cells in the DRAM are non-adjacent.
In a further embodiment, the twisting of the digit lines comprises a modification of a complex twist. Sets of four digit lines are twisted about a point halfway between I/O switches, from inside to outside. In addition to the complex twist, pairs of global column decode lines are twisted about the same point. Further, the I/O switches which are located between the twisted global column decoder lines are coupled to outside ones of the twisted digit lines, and the I/O switches which are located outside the twisted global column decoder lines are coupled to inside ones of the complex twisted digit lines. In this manner, one global column decoder line provides access to four non-adjacent digit pairs which can then be routed with minimal capacitive coupling of the digit lines and very little added complexity. Testing time is significantly cut because there is only one combination of digit lines to test for each global column decoder. All four pairs of digit lines may be tested at the same time rather than individually testing each possible combination of two pairs. In addition, the output from all four pair of digit lines may be taken to I/O pins because of reduced capacitive coupling. Since all four digit lines may be taken from one array, die operating current may be reduced along with a reduction in size and circuit complexity associated with having to obtain data from a different array.
In a further embodiment, four successive adjacent sets of four digit lines are twisted and coupled to pairs of I/O lines as controlled by a pair of twisted column decode lines. The twisting of the digit lines and column decode lines is done about a center point of their run supported by a semiconductor substrate. The sets of digit lines each comprise an inside and outside pair run in parallel on a first side of the center point, and then twisted about the center point such that the inside and outside pairs are reversed. The first and fourth set of digit lines has inside pairs of digit lines coupled to I/O pairs, and the second and third sets of digit lines has outside pairs of digit lines coupled to I/O pairs such that each decode line controls coupling of four different, nonadjacent, digit line pairs to four different I/O pairs.